| contributor | ITI, Rechnerarchitektur |
| creator | Hakmi, Abdul Wahid |
| Wunderlich, Hans-Joachim | |
| Gherman, Valentin | |
| Garbers, Michael | |
| Schloeffel, Juergen | |
| date | 2005-05 |
| description | A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field. Keywords: Deterministic self-test, external BIST, test resource partitioning, test data compression. |
| identifier | http://www.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-117&engl=1 |
| ISBN: ISBN: 0-7695-2314-5 | |
| ISBN: ISSN: 1093-0167 | |
| ISBN: DOI: 10.1109/VTS.2005.50 | |
| language | eng |
| publisher | Institute of Electrical and Electronics Engineers, Inc. |
| source | In: Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS), Palm Springs, CA, USA, May 1-5, 2005, pp. 101-106 |
| subject | Reliability, Testing, and Fault-Tolerance (CR B.8.1) |
| deterministic self-test | |
| external BIST | |
| test resource partitioning | |
| test data compression | |
| title | Implementing a Scheme for External Deterministic Self-Test |
| type | Text |
| Article in Proceedings |